1. Field of the Invention
The present invention relates to one-time user programmable conductor-to-conductor antifuses used in user-configurable semiconductor devices. More particularly, this invention relates to a conductor-to-conductor antifuse structure that avoids the phenomenon of switch-off (or "tread disturb") in programmed antifuses.
2. The Prior Art
Antifuses have been extensively used in Field Programmable Gate Arrays (FPGAs) and other user configurable semiconductor devices for a number of years. One prior art antifuse is made of an oxide-nitride-oxide insulating antifuse layer sandwiched between an N+ diffusion layer and a polysilicon ("Poly") layer (N+/ONO/Poly). Devices according to this design are described in detail in U.S. Pat. Nos. 4,823,181 and 4,881,114. For this class of antifuses, contacts have to be made to the N+ diffusion layer and the poly layer from two corresponding conductive metal lines. This consumes a lot of chip area and introduces additional and unwanted capacitance. Furthermore, the large electrical resistivity of even heavily doped silicon makes the on-state resistance of these antifuses relatively high at about 600 ohms.
A more desirable antifuse would be an antifuse sandwiched directly between two conductive electrodes. Amorphous silicon antifuses and dielectric antifuses between two conductive metal lines have been fabricated. This approach provides a relatively low on-state resistance of about 150 ohms for amorphous silicon and about 80 ohms for dielectric antifuses. A number of patents have issued regarding metal-to-metal antifuse structures. Primarily these patents are directed to teaching how to make low on-state resistance antifuses. See, e.g., Gordon et al., U.S. Pat. No. 4,914,055. Others are directed to low off-state leakage current and low defect density antifuses. See, e.g., Gordon et al., U.S. Pat. No. 5,196,724, and Boardman et al., U.S. Pat. No. 5,120,679. Still others are directed to CMOS low temperature compatible processes. See, e.g., U.S. Pat. No. 5,166,556 to Hsu et al. Some of these patents suggest the use of some of the materials discussed herein in different configurations. For example, U.S. Pat. No. 5,196,724 suggests using TiW electrodes with an amorphous silicon antifuse material; U.S. Pat. No. 5,166,556 suggests using Ti electrodes in conjunction with a relatively thick antifuse layer. Similarly, U.S. Pat. No. 4,914,055 suggests using amorphous silicon as the antifuse material and U.S. Pat. No. 5,166,556 suggests using silicon nitride or silicon oxide as the antifuse material.
Despite the variety of materials and structures suggested by the prior art patents in this field, metal-to-metal antifuses have been unable to achieve wide application-in VLSI technology. The obstacle that has so far prevented metal-to-metal antifuses from being widely applied to VLSI technology is the "switch-off" or "read disturb" phenomenon described by C. Hu ("Interconnect Devices for Field Programmable Gate Array", 1992 I.E.D.M., pp. 591-594) and S. Chiang et al. ("Antifuse Structure Comparison for Field Programmable Gate Arrays", 1992 I.E.D.M., pp. 611-614). For example, S. Chiang, et al., supra, and U.S. Pat. No. 5,166,556 mention that an Al-based electrode is not reliable in this application due to the concern that electromigration might occur. Accordingly, a method of avoiding the switch-off phenomenon in conjunction with the implementation of conductor-to-conductor antifuses in a VLSI architecture would be highly desirable.